Many varied applications exist for techniques for controlling the duty cycles of periodic signals. In some applications, duty cycle control circuitry is required to form essential portions of electronic devices. In other applications, signals of selected duty cycles are utilized to test or evaluate electronic devices. When used for testing purposes, an input signal and an output signal generated by a duty cycle control circuit together form timing signals. The input signal is sometimes referred to as a clock or "stimulus" signal and the output signal is sometimes referred to as a "response" signal. Comparing the relative time of the clock and response signals, provides a basis for evaluating the functionality of the electronic device. Regardless of the application, however, the amount of difference between the input and output signal typically must be selectively and precisely controlled.
In most instances, the input signal is a periodic, clock type signal. Such signal shall hereinafter be referred to as an input clock signal, and the signal generated by the duty cycle circuitry shall be referred to as the output signal.
Conventional duty cycle control circuitry is operative to generate an output signal by introducing a signal delay upon an input clock signal. By generating a signal which is delayed in time relative to the input clock signal, the resultant signal is of a changed duty cycle relative to the input clock signal by an amount corresponding to the amount of signal delay introduced upon the input signal.
Utilizing conventional techniques, the signal delay is introduced upon the input signal by adding electronic gates to a circuit path formed through the circuitry. When the input signal is applied to the circuit path with the electronic gates added thereto, a signal delay is introduced upon the input signal which is of a signal delay amount corresponding to the number of electronic gates added to the circuit path. By increasing the number of electronic gates added to the circuit path, the amount of signal delay, and, hence, duty cycle change, of the signal applied to the circuit is increased.
Conventionally, the input signal is typically formed of a periodic, clock type signal. As the frequency of the input clock signal is increased, the amount of signal delay introduced upon the input signal by conventional circuitry is reduced from the desired amount. For instance, when the input clock signal is of a frequency of approximately one gigahertz, the period of the signal is approximately one nanosecond. A signal delay introduced upon the one gigahertz input clock signal must be on the order of a fractional portion of the one nanosecond period of the input clock signal to cause the resultant signal to be of a desired duty cycle change. At such high frequencies, however, the introduction of a signal delay through the addition of a single electronic gate to the circuit path of such circuitry can result in a signal delay which causes the duty cycle change of the resultant signal to be of a greater than desired amount. Conventional circuitry, which introduces a signal delay upon an input clock signal, is therefore inadequate when input clock signals are of such relatively high frequencies.
Additionally, such conventional circuitry is only operative to change the duty cycle of an input clock signal as a result of the signal delays, and the duty cycle change is permitted only to be of discrete amounts corresponding to signal delays introduced upon the input clock signal by the addition of integer numbers of electronic gates to the circuit path of the circuitry. Such circuitry cannot generate a signal which is changed by duty cycle changes of other than integer numbers of discrete gate delay amounts.
It is with respect to these considerations and other background information relative to duty cycle control circuitry that the significant improvements of the present invention have evolved.